Toshiba MK4006GAH User Manual Page 130
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11.8.45.3.1.3 Word 2: Ultra DMA modes supported
Word 3 bits 5-0 contain the same information as contained in word 88 of the IDENTIFY DEVICE or IDENTIFY
PACKET DEVICE command response. Bits 15-6 of word 3 are reserved.
11.8.45.3.1.4 Words 3-6: Maximum LBA address
Words 4 through 7 define the maximum LBA address. This is the highest address accepted by the device in the
factory default condition. If no DEVICE CONFIGURATION SET command has been executed modifying the
factory default condition, this is the same value as that returned by a READ NATIVE MAX ADDRESS or READ
NATIVE MAX ADDRESS EXT command.
11.8.45.3.1.5 Word 7: Command/features set supported
Word 7 bit 0 if set to one indicates that the device is capable of supporting the SMART feature set.
Word 7 bit 1 if set to one indicates that the device is capable of supporting SMART self-test including the
self-test log.
Word 7 bit 2 if set to one indicates that the device is capable of supporting SMART error logging.
Word 7 bit 3 if set to one indicates that the device is capable of supporting the Security feature set.
Word 7 bit 4 if set to one indicates that the device is capable of supporting the Power-up in Standby feature set.
Word 7 bit 5 if set to one indicates that the device is capable of supporting the READ DMA QUEUED and
WRITE DMA QUEUED commands.
Word 7 bit 6 if set to one indicates that the device is capable of supporting the Automatic Acoustic Management
feature set.
Word 7 bit 7 if set to one indicates that the device is capable of supporting the Host Protected Area feature set.
Word 7 bit 8 if set to one indicates that the device is capable of supporting the 48-bit Addressing feature set.
Word 7 bits 9 through 15 are reserved.
11.8.45.3.1.6 Words 8-254: Reserved
11.8.45.3.1.7 Word 255: Integrity word
Bits 7:0 of this word shall contain the value A5h. Bits 15:8 of this word shall contain the data structure checksum.
The data structure checksum shall be the two’s complement of the sum of all byte in words 0 through 254 and
the byte consisting of bits 7:0 of word 255. Each byte shall be added with unsigned arithmetic, and overflow shall
be ignored. The sum of all bytes is zero when the checksum is correct.
11.8.45.4 Device Configuration Set
COMMAND CODE
1 0 1 1 0 0 0 1
REGISTER
REGISTER SETTING NORMAL COMPLETION
DR DRIVE No. no change
CY na no change
HD na no change
SN na no change
SC na no change
FT C3h no change
LBA na no change
- TOSHIBA 1
- MK6006GAH/MK4006GAH 1
- /MK3006GAL 1
- Revision History 2
- IMPORTANT MESSAGES 3
- LIMITATION OF LIABILITY 3
- USAGE RESTRICTIONS 4
- TABLE OF CONTENTS 7
- Table of Figures 10
- 2. SCOPE 11
- 3. GENERAL DESCRIPTION 11
- Page 12 of 153 12
- 4. KEY FEATURES 13
- 5. BASIC SPECIFICATION 15
- 6. PERFORMANCE 16
- 7. POWER REQUIREMENTS 17
- 8. MECHANICAL SPECIFICATIONS 18
- 8.3.1 Installation 19
- MK3006GAL Dimensions 20
- 9. ENVIRONMENTAL LIMITS 22
- 9.4 Altitude 23
- 9.5 Acoustics 23
- Sound Power 23
- 9.6 Safety Standards 24
- EMC Adaptability 25
- 9.7 Magnetic Fields 25
- 10. RELIABILITY 26
- 10.6 Load/Unload 27
- 11. HOST INTERFACE 28
- 11.2.2.1 Input 29
- 11.2.2.2 Output 29
- 11.3 Interface connector 30
- 11.3.2 Pin Assignment 31
- 11.3.3 Signal Treatment 32
- 11.3.4 Series resistance 33
- 11.3.5 Signal Description 33
- 11.4 Host Interface Timing 35
- 11.5 Grounding 48
- 11.6 Address Decoding 49
- 11.7 Register Description 50
- 11.7.2 Error Register 51
- 11.7.2.1 Operational Mode 51
- 11.7.2.2 Diagnostic Mode 51
- 11.7.7.2 SMART commands 54
- 11.7.8 Device/Head Register 54
- 11.7.9 Status Register 55
- 11.7.10 Command Register 56
- Command Code 57
- 11.8 Command Descriptions 60
- 11.8.1 Nop (00h) 61
- 11.8.2 Recalibrate 61
- (1xh) 61
- 11.8.3 Flush Cache (E7h) 61
- 11.8.9 Read Verify (40h) 64
- 11.8.11 Write Verify 65
- (3Ch) 65
- 11.8.12 Format Track 65
- (50h) 65
- 11.8.13 Seek (7xh) 66
- 11.8.14 Toshiba Specific 66
- 11.8.18 Read Multiple (C4h) 69
- 11.8.23 Read DMA (C8h/C9h) 73
- 11.8.25 Write DMA (CAh/CBh) 74
- 11.8.27 Power Control (Exh) 75
- 11.8.27.3 Stand-by (E2/96) 76
- 11.8.27.4 Idle (E3/97) 76
- 11.8.27.6 Sleep (E6/99) 76
- 11.8.28 Read Buffer (E4h) 77
- 11.8.29 Write Buffer (E8h) 77
- 11.8.31 SET MAX (F9h) 91
- 11.8.31.1 Set Max Address 91
- 11.8.31.3 Set Max Lock 92
- 11.8.35 Set Features (EFh) 96
- Sector offset(15:8) 121
- 11.9.4 Password lost 137
- 11.9.5 Command Table 138
- 11.10.1 Attributes 139
- 11.10.2 Attributes values 139
- 11.11.1 Performance Idle 140
- 11.11.2 Active Idle 140
- 11.11.3 Low Power Idle 140
- 11.11.4 Transition time 140
- 11.12 Reset 141
- 1 C A 142
- 2 D B 142
- 11.14 Cache Memory 143
- 12. Protocol 144
- 12.1 PIO data in commands 145
- 12.2 PIO data out commands 145
- 12.3 Non-data commands 147
- • READ DMA EXT 149
- • WRITE DMA EXT 149
- 12.5 Ultra DMA 150
- 12.6 Other timings 153
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